MRAlpha High Level Software Design



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Software Organization


System Architecture

The D2W system consists of six main software components:

Additional components:

  • Scripts

  • Utilities

Activities

UI elements; may call sequences.

Processes

High-level orchestrators; can invoke activities and sequences.

Subsystems

Subsystems are divided into:

  • Logical Subsystems: Inherit directly from the Subsystem class; allow simulation.

  • Hardware Subsystems: Wrappers for hardware libraries; inherit from hardware abstraction classes such as:

    • Motion Controller

    • IO Controller (digital lines and pneumatics)

    • Cameras

    • Sensors

Subsystem Development Process

  1. Define Hardware

  2. Create Hardware Control Library

  3. Create Subsystem for the hardware

  4. Create Manual Control Process and Activity

  5. Test with Hardware

  6. Integrate into higher-level system

  7. Add to D2W Manual Control (create Tab)

  8. Test Integration

  9. Create Activities and Automated Sequences

  10. Process Testing

System Architecture Diagram

Material Tracker

Material tracker is a logical subsystem that tracks the materials in the machine

Material

Locations in D2W

Material Path

Notes

Tape-Frame

Tape Frame chuck (TFC)

EFEM ->TFC -> EFEM

Is both a location and a material

Face Up Wafer (FUW)

Wafer chuck (WC)

EFEM → WC-> EFEM

Is both a location and a material

Face Down Wafer (FDW)

FUW (jig)

ZHead

FUW

EFEM -> FUW(jig) ->  ZHead -> FUW


Die


Tape-Frame (position array)

FUW (position array)

Die carriage

ZHead

Tape-Frame -> Die Carriage -> ZHead -> FUW


Sequences

Automated, ordered machine actions; no user input.

Process Overview


Software Release Process

Automated builds are deployed from the main branch of MRAlphaController via Github CI pipeline. They are stored in an S3 bucket.

  • You can also build a deployable binary via buildtool in the MATLAB cmd line.

  • We place released software builds on the CR lab computer in C:/Software/MRalpha_latest_release/ directory.

  • We place untested development builds on the CR lab computer in C:/Software/MRalpha_latest_dev/ directory.

  • We expect this release process to be automated further as we get closer to production level code.

Wafer Bond Process

State Table

Action


Wafer Chuck


ZHead


Face Up Wafer

Notes

Initial State


FUW 0


FDW 0


FDW 0


  1. Load a Face-Up wafer (jig)

->

FUW 1


FDW 0


FDW 0


  1. Load a face down wafer


FUW 1


FDW 0

->

FDW 1

It has the jig

  1. Transfer FDW to ZHead


FUW 1


FDW 1

<-

FDW 0


  1. Unload Wafer Jig

<-

FUW 0


FDW 1


FDW 0


  1. Load normal FUW

->

FUW 1


FDW 1


FDW 0


  1. Bond 


FUW 1


FDW 0

->

FDW 1

Bonded

  1. Unload bonded wafers 

<-

FUW 0


FDW 0


FDW 0


Diagram