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I’m hoping to be able to run the converter at about 2 MHz. Maximizing frequency will allow me to use the smallest passive components possible.
tes = Switch A and B on
tdir = Switch A on, B off
tind = Switch A and B off
tres = resonant reset period (half of switching period)
ex:
tes = 40ns
tdir = 20ns
tind = 20ns
tres = 80ns
period = 160ns
Spice Parameters:
Minimize capacitor values
Maximize frequency
TODO:
Write script to characterize duty cycle and frequency of both operating modes.
Figure out what’s wrong with my sim
Find frequency with max power output. Can probably operate at a much higher frequency than I thought because of the relatively low output voltage compared to the input.
Timing Circuitry
Identical circuits for SA1 and SB1:
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The input of the comparator will need to be able to consider 63.2% of the 5v as a signal high so that I can just use the time constant of the RC circuit and not have to mess around with characterization. If this isn’t precise enough I may have to calibrate this manually to get the timing right.
The DAC to generate the V_TMR will need to be very precise since the timing is on the ns scale. A discrete DAC may be preferred over the Nucleos integrated DAC.
I think i’m pretty close to making a layout and printing this board. I may also just make it on a breadboard bc the components are mostly passives that I can control with my MSPM0 microcontroller and read with an oscilloscope.
Engineering Diary
Check out Dr. Hanson's paper on a ZVS resonance converter design he made:
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