2024 - 2026 USB-C PD Dongle Design Document

Research/Design

Objective:

The purpose of this board is to be able to use a USB Type-C laptop charger to run one LV system (such as BPS or Controls). The dongle will act as a breakout; negotiating the power delivery at a fixed voltage with the laptop charger and delivering as much current as needed at a stable voltage of 12V/5V.

The dongle will (hopefully) also be able to supply the maximum amount of current necessary for any of our systems. @Lakshay Gupta wants to be able to handle the current spike that BPS has when the HV+, HV-, and HVARR contactors flip, so the design should potentially accommodate for that.

Requirements:

• Simultaneous 12V and 5V output at max amperage possible

  • 12 for LeaderSOM, 5 for PeripheralSOM

• Status LEDs

• On/off toggle switch

• Current/voltage monitoring capability

• Overcurrent/voltage and undervoltage protection

Preliminary Research Notes:

• USBPD devices can either act as the source (charger) or sink (device) or DRP (both). For our purposes we probably want a sink-only chip since we'll be plugging a charger into this board and the output will be a 12V/GND line. We don't need this to act as a source from a wall outlet.

• Compatibility with USBPD 2.0 and USBPD 3.0 would be nice to allow us to use a wider array of laptop chargers.

  • USBPD 2.0 allows for fixed voltage outputs of 5, 9, 12, 15, and 20V

    • USBPD 3.0 allows for incremental voltage outputs anywhere from 3.3V to 21V in increments of 20mV. This is called PPS (programmable power supply). We don't really need this since we only need to provide fixed 12V and 5V.

• Perhaps considerations should be made for USBPD 3.1 as well, as that would allow for a higher power delivery of 240W and possibly support driving contactors.

  • 3.1 is backwards compatible so designing a 3.1 sink should allow for interfacing with 3.1/3.0/2.0 source

  • Since we want to max out current I think 3.1 makes the most sense as USBPD 3.1 EPR (Extended Power Rating) cables have the capability of providing up to 240W @ 48V

    • This may have to wait as there are not many 3.1 sink chips available

    • According to this reddit post, USBPD3.1 @ 240W probably isn't possible since the sink functionality of it is not well supported. I took a look at a few chips such as ST-ONEHP and TPS25730USB.

USBPD Controller Chip Evaluations:

• Mouser USBPD Search

• USB Type-C PD 3.0 Specification, Charging and Design

• Guide to USB-C Pinout and Features

• USB Type-C and USB power delivery power path design considerations

• Phil's Lab video

• Designing a USB PD (Power Delivery) Trigger Board For My Devices

• Infineon CYPD3177-24LQXQT

  • Used in this Phil's Lab video

  • In stock on Mouser as of 5/22/24

  • Price: $2.20

  • Operates on USB-PD 3.0 Standard

  • Capable of 100W (20V @ 5A)

  • Evaluation Kit Guide

  • Open

    

  • Pretty simple to set VBUS Min/Max and Current Min/Max; just use voltage dividers on four config pins as shown above

  • Offers a fault indicator

  • Falls back to 5V in case negotiation fails

  • QFN package (more difficult to solder, but still manageable at Pickle esp. with someone with experience)

• INJONIC IP2721

  • Used in this isaac879 video

  • Available for order on JLCPCB or AliBaba

  • In-stock at JLC and Alibaba as of 5/8/24

  • Price: $0.69

  • Capable of 20V

  • Connecting high to SEL pin will make it output 20V, which makes configuration easy

  • The downside of this (as according to this Hackaday post) is that even though USB-PD supports current negotiation (sink asking source what current it supports), the IP2721 doesn't. So if a charger is plugged in that doesn't support 5A, which we are ultimately going to request, then we still may not get the current we want and perhaps trigger some overcurrent condition on the source if we go over that amount.

  • TSSOP package, so easier to solder

• Texas Instruments TPS25730

  • Price: $2.69

  • On backorder in Mouser as of 5/8/24

  • In TI's product selector for USBPD chips, this seems like the newest sink-only chip

  • It supports PD 3.1 in that you can do PPS (which we don't actually need anyways)

  • Capable of 100W (20V @ 5A)

  • It looks like an external microcontroller can be attached to I2C for configuration purposes, but doesn't have to be

  • Open

    

  • Min/max voltage and operating current/max current configured through ADC1 through ADC4, can just hook up voltage divider

  • TPS25730D has an internal HV path, whereas S has a gate driver for an external HV path

  • QFN package; harder to solder as mentioned before

• STMicroelectronics STUSB4500

  • In-stock as of 5/8/24

  • Price: $2.71

  • Reference schematic

  • Capable of 100W (20V @ 5A)

  • Configurable through programming non-volatile memory (NVM) through I2C

    • Would make initial configuration of anything above 5V a bit more difficult, but would only need to be done once at the beginning with a programmer of some sort (Nucleo?)

  • QFN package

Buck Converter Research:

• I suppose we'll need a high-efficiency buck converter to step down from max 20V@5A to 12V@8.333A after the whole USB PD negotiation is complete.

• Another design consideration was made in this area about the buck converter pipeline. The two possible options were 20V → 12V → 5V (e.g. having chained buck converters) or 20V → 12V AND 20V → 5V (independent buck converters)

  • Chaining buck converters means that we can use the same 12V → 5V buck converter we typically use, muRata MYLSM00502ERPL. However, this means that if 12V or above is not in a source’s capabilities, then 5V will also fail. Basically 5V is entirely dependent on the 12V working, which limits the set of USB Type-C chargers we can use with this board.

  • Independent buck converters means that 5V can function without 12V, so if a PD charger WITHOUT 12-20V support is used, we can still test a low voltage device. This seems better but also makes our job as circuit designers more difficult in terms of validation, cost, or efficiency.

• Matthew Yu’s notes on LDO vs Buck Converters:

• Tips on Layout from Phil's Lab

• Buck Converter Explained

  • Another one: Buck Converter 2: Electric Boogaloo 

  • Other typical forms of voltage step-down (Linear Voltage Regulator (LDO), Voltage Divider) dissipate power as heat to step down voltage. We lose power in some capacity as heat.

  •  Buck converters will decrease voltage AND increase current to maintain power (typically higher efficiency but less stability when compared to an LDO)

    • When the switch is closed, the inductor charges up

    • When the switch is opened, the inductor releases charge through the load resistor RL. The current flows through the diode and back into the inductor

    • We switch the switch (MOSFET) at a certain frequency and duty cycle in order to keep the average current relatively stable over one period

    • The capacitor is assumed to have a steady voltage over one period, so it just keeps the voltage drop across RL the same

    • Watch the Buck Converter 2 video for more explanation and the derivation for the following equation:

      • Vout = Duty Cycle x Vin (typically)

      • Datasheet will have more specific calculations for things such as voltage dividers which will ultimately set the duty cycle

    • A synchronous buck converter replaces the diode with another MOSFET so that there is less power loss since the MOSFET will have lower power loss while current is flowing thru it

• Luckily for us, these buck converters come in convenient little ICs that will do all this switching for us

  • We need two of these, one for 12V and one for 5V

  • WEBENCH Power Designer

  • Integrated FET packages (the mosfet comes inside the IC)

    • Mouser Filter Link

    • TI Filter Link

    • Analog Devices Filter Link

      • Nothing on here that can do more than 6V output

    • TI TPS56A37

      • $2.87 on Mouser

      • 4.5V to 28V input

      • 0.6 to 13V output

      • Supports 10A continuous output current

      • Seems most appropriate for our 20V->12V use-case especially since other ICs can't supply as much current

      • QFN package

    • Analog Devices ADP2303ARDZ-5.0-R7

      • $4.08 on Mouser (we can do better on price)

      • 3 to 20V input

      • 5V output

      • 2/3A

    • TI TPS62933ODRLR

      • $0.99 on Mouser

      • 3.8 - 30V input

      • 5V output

      • 3A

      • 12 uA quiescent current

      • @Champers Fu approved!

      • This one is really good, perhaps we should use it for more designs

  • External FET Buck Controller packages also exist and were looked into briefly (mosfet is outside the IC, might be more cost-effective and able to provide enough current)

    • TI Filter Link

    • TBH I kind of prefer an integrated package rather than this so might not really look at these any further

• Is isolation required between the USB-PD provided power and the device power?

  • If so, an external FET buck controller package with a transformer may be required

  • https://www.eevblog.com/forum/projects/usb-type-c-pd-lab-power-supply/

  • Decided it's probably not worth it. From what I can tell from online + talking to Jacob Pustilnik and Matthew Yu, isolation is mainly used to protect the user from voltage shock and to protect the device from taking a large amount of voltage if the buck converter fails. Additionally, the cost difference after looking at some Murata buck converters is large enough to warrant no isolation ($83 is a LOT). We'll just A) be safe when using the device, perhaps put it in an enclosure of some sort, and B) make sure that there is voltage protection on new devices we produce so that a 5V device like the Peripheral SOM won't break if a spike of 20V is applied to it. We'll also include some overvoltage protection on the output to make sure this doesn't output more than 12/5 V.

Input Voltage Range

• Originally the decision was made to have two buck converters both bucking from the source voltage of 5-20V. The reason this decision was made early on was because a heavy emphasis was being placed on this board working with a wide range of USB PD chargers for a larger applicability.

  • If your source charger doesn’t support anything from 12-20V, and only supports something 9V or lower, you could still originally operate on the 5V output.

• However, this decision needs some reconsideration. First, an argument could be made for not supporting anything other than 20V.

  • 12V isn’t typical on these laptop chargers and is usually considered an “optional” voltage

  • While it would be cool to run on 5V/9V chargers, perhaps the design considerations necessary for them (such as a 5V buck bypass mosfet in case the voltage input is 5V to prevent voltage dropout, or a similar design on the 12V buck for an input 12V) isn’t worth it.

  • Most common is the 65W USB-C laptop charger, which usually is 20V at 3.25A (bucks down to approx. 12VV at 5.41666667A).

  • We could even buy a few of these Anker 100W USB PD chargers for people to use with the device.

• Additionally, supporting a wider range of voltage inputs is making development slightly more difficult for not all that much gain.

  • Supporting 5V and 12V requires us to have a bypass MOSFET around the buck converter in order to not lose a lot of power (12V into the 12V buck converter will not output 12V, and similarly with 5V).

• All in all, a larger variety of chargers supported may just make our lives harder. Thus, let’s decide to make it only operate if the USB-PD charger supports 15 or 20V.

Buck Converter Pipeline

• If 15/20V is set as a required voltage, the buck converter pipeline can also be reconsidered.

  • Instead of two parallel bucks, one to 12 and one to 5, we could have 15/20V → 12V → 5V and chain bucks. See Matthew’s notes on this above.

• Let’s assume that the buck converters we are using are still TPS56A37RPAR and TPS62933PDRLR.

• I plugged two different configurations of the TPS62933P into WEBENCH, TI’s automatic designing tool, to test out which was better for efficiency of the buck converter

  • The first was a buck from 14.25-21V down to 5V, to simulate the buck to 5V directly from the source at the lower and upper bounds that USB PD provides. This resulted in a steady state efficiency of 89.5%.

  • The second was a buck from 11.4-12.6V down to 5V, to simulate the buck to 5V after daisy-chaining with the previous buck converter. This resulted in a steady state efficiency of 92%.

  • However, this doesn’t necessarily mean the daisy chaining is better. According to this stack exchange article I found, the efficiency will be multiplied if buck converters are chained.

• Steady state efficiency of the TPS56A37 on WEBENCH is 97.1% at 3A

  • So, if daisy chained, the overall efficiency of the 5V output would be 89.332%, very slightly lower than the steady state efficiency found for the 15-20V → 5V buck configuration.

  • This conclusion doesn’t really convince me that either one is better/worse.

  • Also, this is at worst-case conditions, so it could tip in favor of one or the other at nominal conditions

Block Diagram:

PMOS Power Switch Configuration:

(Infineon CYPD3177-24LQXQT)

Question: What does this even do?

Answer:

• https://www.homemade-circuits.com/bidirectional-switch/

• TLDR; even if a MOSFET is not powered via the gate, the diode can still carry current if it flows into the gate. This double MOSFET configuration prevents current from flowing either way, so there is no power loss across the diode when inactive.

  • If both MOSFETs are on then current can pass either way, but if both are not on current cannot flow at all due to the diode.

  • Bidirectional switch

Let's try to understand the configuration (this is a slightly more detailed version with specific part numbers as presented in the Evaluation Board Design):

• SAFE_PWR_EN (or as referenced here SAFE5V_FET_EN) is driven to 0V if negotiation fails and USB PD falls back to 5V at 1A. Otherwise it is high impedance.

• If negotiation fails, VBUS_OUT = 5V and SAFE_PWR_EN = 0V. The voltage divider drives the MOSFET's gates at ~0.098V.

  • When negotiation fails, the common source node (where S1 connects to S2 on the diodes) will be equal to VBUS_OUT (5V).

  • Therefore, V_GS = 0.098 - 5 = -4.90200 V

  • As according to the datasheet, V_GS(th) = -1.5V. Remember, since this is a P-channel MOSFET, it gets activated with a negative V_GS.

  • So V_GS > V_GS(th), therefore the gate of both MOSFETS will allow current to flow and SAFE_5V_OUT will get 5V.

• Why do we need the 49.9k and 1k resistors?

  • The 49.9k really acts more like a large pull-up resistor rather than a voltage divider from what I can tell. If negotiation of USB-PD succeeds, SAFE_PWR_EN is high impedance. This means that it will be easily influenced by whatever is connected to it, so it can be pulled up/down. Then, VBUS_OUT pulls it up to its voltage so that the gate is not triggered (since then source = gate)

    • This sort of pull up resistor from gate to source is common as protection circuitry in case the gate pin goes floating or gets fried or something. It will ensure that the gate goes to 0V if the pin goes high impedance.

  • The 1k is for protecting the gate inputs to the MOSFETs (see https://www.build-electronic-circuits.com/mosfet-gate-resistor/)

• Make sure that the sources are connected

  • For this sort of configuration, the sources need to be at the same voltage level since you want to control the gates via the same line. The MOSFET chooses to turn on when the gate-source voltage is above V_GS(th) , so the source reference needs to be the same in both a PMOS or NMOS config.

A similar configuration is used for the main output of the board as well. The reason we use a PMOSFET controlled switch for VBUS_OUT instead of just directly outputting to the sink is shown below (see pg 10 of Evaluation Board Design)

TPS56A37RPAR Buck Converter Calculations (15/20V → 12V):

See section 7.2.2 of the datasheet linked above.

• Undervoltage lockout calculations (see datasheet pg 13)

  • Vstart = 14.25V

    • According to this, the tolerance of USB PD with a fixed voltage charger (non PPS) is about 5%

  • Vstop = 12.75V

    • This was the highest I could go before R1 became negative

  • R1 = (14.25V x (1.07/1.18) - 14V)/(1uA x (1 - (1.07/1.18)) + 3uA) = 55.5 kOhms

  • R2 = (55.5 kOhms x 1.07V)/(12.75V - 1.07V + (55.5 kOhms x (1uA + 3uA)) = 4.99 kOhms

  • Ven = (1390.20537 ohms x 25V + (55.5 kOhms x 4.99 kOhms x (1uA + 3uA)))/(55.5 kOhms + 4.99 kOhms) = 0.5929V < 5.5V

• R6/R7 calculations for output voltage

  • Vout = 0.6 x (1 + R6/R7)

  • Vout = 12V

  • R6/R7 = 19

• Using Table 7-2, recommended values are as follows for Output Voltage and Output Filter selection:

• Note: for this next set of calculations, I referenced this presentation and chose a safety factor for Vin of about 20%.

• Equation 8 (inductor peak-to-peak ripple current):

  • Il_p-p = 12V/24V x (24V - 12V)/(5.6uH x 500kHz) = 2.14285714 A

• Equation 9 (peak current)

  • Il_peak = 10A + 2.14285714 amperes/2 = 11.0714286 amperes

• Equation 10 (RMS current)

  • I_LO(RMS) = sqrt(10^2 + 1/12 + (2.14285714)^2) = 10.2310884 A

• When choosing an inductor, it seems like we want to pay attention to the following things:

  • Inductance must be as specified (5.6 uH)

    • SRF (self-resonant frequency) should be a good amount (at least 10x) higher than the operating frequency (500kHz)

  • Saturation current should be higher than peak current + ripple current, since as soon as the inductor reaches the saturation current it will drastically decrease in inductance (see this)

    • https://electronics.stackexchange.com/questions/538382/inductor-core-saturation-dc-vs-peak-current-value

    • In our case, a saturation of >= 14 A seems appropriate

  • Rated current should be >= the typical DC current to make sure the inductor doesn’t heat up too much.

  • A shielded inductor keeps stray magnetic fields from screwing up your circuit

  • With all of that in mind, by filtering on Mouser, I was able to find a few Bourns inductors.

  • By far, the best characteristics on any of these was the Bourns SRP1270-5R6M

    • 5.6 uH

    • Saturation Current of 26.5A (as specified on the datasheet, inductance drops 30% at the saturation current)

    • 13MHz SRF

    • $1.55 on Mouser

    • By comparing the graphs, I was able to determine that this inductor heated up the least and dropped in inductance the least as higher and higher currents were applied, as opposed to some of the other Bourns options

• Equation 11 (rms current rating for output capacitor) (C5/C6 on diagram, Cout in table)

  • Note: choosing max Vin of 25V for safety factor

  • I_CO(RMS) = (12V x (24V - 12V))/(sqrt(12) x 24V x 5.6uH x 500kHz) = 0.618589574 amperes

  • Capacitor value is 2 22uF ceramic caps as listed in table above

• Equation 12 (input voltage ripple)

  • C3’s voltage rating must be greater than the max input voltage, which is the max input voltage + any voltage input ripple. Voltage ripple is calculated as follows:

  • Vin = (13.2142857 A x 0.25)/(20.1uF x 500kHz) = 0.328713575 volts

  • Note that Cin = 20.1uF here since the total input capacitance on the input is two 10uF caps and one 0.1uF cap

  • So maximum Vin = 20V + 0.27V = 20.27V

• Equation 13 (input cap current ripple)

  •  

  • I_CIN(RMS) = 10A x sqrt(12V/14.25V x (14.25V - 12V)/14.25V ) = 3.64642275 amperes

• Ensure that 0.1uF bootstrap capacitor (C4) has 10V or higher voltage rating, ceramic capacitor with X5R or better dielectric

TPS62933PDRLR Buck Converter Calculations (15/20V → 5V):

See datasheet linked above, as well as the section above this one.

• Output voltage calculation

  • Rfbt = (5V - 0.8V)/0.8V x 10kOhms = 52500 ohms (51k and 1.5k)

• Switching frequency will be 500kHz so that power loss is minimal, so RT will be floating

• Undervoltage lockout on EN pin

  • Vstart = 14.25V

    • According to this, the tolerance of USB PD with a fixed voltage charger (non PPS) is about 5%

  • Vstop = 13.5V

    • This was the highest I could go before R1 became negative

  • R1 = (14.25V x (1.17V/1.21V) - 13.5V)/(0.7uA x (1 - 1.17V/1.21V) + 1.4uA) = 200 kohms

  • R2 = (200 kohms x 1.17V)/(13.5V - 1.17V + 200 kohms x (0.7uA + 1.4uA)) = 18.35 kohms

  • Ven = (18.35 kohms x 24V + (200 kohms x 18.35 kohms x (0.7uA + 1.4uA)))/(200kohms + 18.35 kohms) = 2.0522 V < 5.5V

Inductor selection (starting pg 30 of the datasheet):

• Peak-to-peak ripple current and inductance

  • Note: choosing max Vin of 24V for safety factor (20% above intended voltage)

  • L = (24V - 5V)/(500kHz x 0.4 x 3 A) x (5V/24V) = 6.59722222 uH

  • 🔺IL = 5V/24V x (24V - 5V)/(6.59722222 uH x 500kHz) = 1.2 A

• Maximum Inductor peak current

  • IL_Peak = 3A + 1.2A/2 = 3.6A

• RMS current

  • IL_RMS = sqrt((3A)^2 + ((1.2A)^2)/12) = 3.01993377 A

• IHS_LIMIT = 5.8A (make sure inductor sat current is higher than this so that in case of a short across high side mosfet it doesn’t saturate)

• Nearest standard value available is 6.6uH, so we must recalculate K

  • 6.6uH = (24V - 5V)/(500kHz * K * 3A) x (5V/24V)

  • K = (24V - 5V)/(500kHz * 6.6uH * 3A) x (5V/24V) = 0.4 🤷🏽

  • K value is the ripple ratio of the inductor current (🔺IL/Iout_max)

• sumida CDR10D48MNNP-6R6NC

  • 6.6uH

  • Saturation current of 7.1A

  • Temperature rise current of 5.7A, well over what we’re drawing

Input Capacitor Selection

• Use values of 10uF + 10uF (decoupling) and 0.1uF for high frequency filtering as recommended in example design (see pg 32)

• Reference datasheet when actually selecting parts for notes on specs

Output Capacitor Selection

• Output capacitor directly affects voltage ripple, loop stability

• Output voltage ripple comprised of:

  • Inductor current ripple going through ESR of output caps

  • Inductor current ripple charging/discharging output capacitors

  • with K being the ripple ratio of the inductor current (see above) assumed to be 40%.

  • Assume output ripple is targeted at +- 20mV. So, 🔺Vout_esr = 20mV and 🔺Vout_c = 20mV. Note this does not mean the actual ripple is 40mV, as these are separate ripples that will be out of phase, so average voltage ripple will be < Vout_esr + Vout_c

  • 20mV = 0.4 x 3A x ESR → ESR = 16.67 milliohms at maximum

  • 20mV = (0.4 x 3A)/(8 x 500kHz x Cout) → Cout = (0.4 x 3A)/(8 x 500kHz x 20mV) = 15uF at minimum

• Additionally, the output caps are what provide the required charge while waiting on the inductor to rise to the expected current. “Thus, the output capacitance must be high enough to supply the current difference for about eight clock cycles to maintain the output voltage within the specified range.” - (pg 31 of datasheet)

  • The 🔺Vout is specifically the change in voltage for over/undershoot that we are ok with on some 🔺Iout load step (e.g. some change in desired current).

  • D is the duty cycle (Vout/Vin)

  • I suppose it can’t hurt to use the same specs as the example design and adjust if necessary.

  • For 24V input (includes safety factor of 20%): Cout >= (1.5A)/(500kHz x 250mV x 0.4) x [(1 - 0.208333333) x (1 + 0.4) + ((0.4)^2)(2 - 0.208333333)/12] = 34uF

• Minimum capacitance of 32.2uF for 5% overshoot at 1.5A load step

• Maximum ESR of 16.67 milliohms for 20mV voltage ripple

• Be careful here with part selection; depending on the ceramic capacitor(s) chosen, the caps will have DC bias de-rating. This means the effective capacitance will decrease at higher DC voltages. Check the datasheet to see how much the capacitance decreases at expected voltage of 5V, and adjust the chosen capacitors accordingly.

  • We typically use the 0805 size as our standard passive component package for our boards, so I’ll filter for that on Mouser. Also assuming that we’ll use some combination of 10, 15, and 22uF caps for this output.

  • I looked at a few different characteristic graphs of different 22uF caps first (see the design tips section below to see how I found these graphs), most seemed to average around 50% effective capacitance at 5V. Decided to settle for this 22uF Murata Cap (GRT21BR61E226ME13L) which has a effective capacitance of 10.21uF (see graph below and this link) at 5V. We can tack on 3 of these to get ~30.63uF. Rated voltage of 25V.

  • Next we’ll tack on a few 10uF caps to get above the 32.2uF threshold. The Standardized Components Sheet we keep on the club’s Sharepoint references TMK212BBJ106MGHT, a TDK 10uF cap that we commonly use. The DC bias curve shows a 38.229% drop in capacitance at 5V. This means an effective capacitance of ~6.177uF. That should be enough for our purposes.

  • In total, we have an effective output capacitance of 36.807uF, which is hopefully and probably fine. Worst case scenario we can choose to remove some of them if the performance is poor due to too large output capacitance.

Current Monitoring

Initial Research

• What is a shunt resistor?

  • The general principle is that measuring the voltage drop across a known value resistor (shunt resistor) will give you current.

  • Since I = V/R, measuring the voltage drop and dividing it by the resistance value will give you the current.

  • This voltage drop across the resistor can also be fed into a differential amplifier, magnifying the voltage drop to a reasonable level (since a shunt resistor tends to be a lower value, so less voltage drop).

• The plan is to use a shunt resistor and a current sense amplifier and feed the output to a couple of pins, test points, or a connector (haven’t decided yet). This could then be measured by an oscilloscope and logged so that current monitoring is possible.

• After some deliberation, I decided that it would be cool to add a seven segment display to the board in order to display the amount of current on the 12V bus or 5V bus.

• There are two strategies to implement this:

  • Use a specialized IC to convert the analog voltage produced by the shunt resistor +amplifier into an output that can be read by a seven segment display.

  • Program a microcontroller with an integrated ADC to convert the analog voltage into an output.

  • Much of the time, the second solution can be more cost effective and configurable than the first.

Microcontroller & LCD Selection

• If we are measuring current on the 12V and 5V bus, we will need two integrated ADCs. These will come in anywhere from 8-24 bit resolution.

• Let’s think about the display, since that may be the constraining factor on resolution displayed anyways. I kind of want to use this 4-digit seven segment display I found on Mouser. It’s about $2.55.

  • Be careful. Almost selected a 5V A.C. seven segment display rather than a D.C. one.

  • It has LEDs for decimal points as well!

  • For the 5V bus, since current goes from 0 to 3A, it would be nice to display current as X.XXX A. This implies a resolution of maximum 0.001A, or 1mA.

  • The 12V bus will be lower resolution since we have to display a range from 0 to 10A. Thus, we will display current as XX.XX A. This implies a resolution of 10mA.

• Next, the number of pins. Our MCU will need 1 pin for an ADC and some pins to interface with the selected seven segment display.

  • Note that on the datasheet we are presented with a schematic:

  • This brings total I/O to 17 pins. Also note that forward voltage is 2.6V at max, which means we’ll probably need to add some resistor in series to ensure that the output of our MCU is not too much for it to handle. Similar thing with current.

• One more thing to note is that we can power this off the 5V bus to reduce voltage conversion bullshit, which means we’re looking for something that can handle a supply voltage of 5V.

• Also, no QFN packages please 🙏🏽 (we already have enough on this board).

• This brings us to our product of choice: the ATTINY826-XU

  • Datasheet

  • 18 I/O pins

  • 12-bit ADC at 375 kilosamples per second, or 17-bit ADC with oversampling

  • USART supporting one-wire mode (which is both something we’re constrained by as we only have one extra pin, but also we don’t really need RX capability only TX to output data to UART)

• Let’s do the math to see if the resolution is fine for our four digit display

Shunt and Amplifier Selection

• First, let’s figure out where to put the shunt resistor: https://www.allaboutcircuits.com/technical-articles/resistive-current-sensing-low-side-versus-high-side-sensing/

  • To do this, let’s talk about CMRR (Common Mode Rejection Ratio). Here’s Google’s Gemini AI engine to help (prompt: Explain CMRR and what a common vs differential mode signal is of an op-amp to me with an analogy like I am 15 years old):

    • Imagine you're at a concert with your friend. The band is the desired signal you want to hear clearly.

      • Common-mode noise is like a bad sound system rumble that affects both of you equally. It might be caused by a loose wire or some electrical gremlins.

      • Differential-mode signal is the actual music from the band. This is what you want to amplify without the rumble.

    • An op-amp is like a fancy headphone amplifier that boosts the music (differential signal) for you and your friend. Ideally, it should completely ignore the rumble (common-mode noise).

      • CMRR (Common Mode Rejection Ratio) is how good the op-amp is at ignoring the rumble. A high CMRR is like having high-quality headphones that block out most of the rumble, leaving just the clear music.

    • In reality, no headphones are perfect, and some rumble might still leak in. Similarly, even a good op-amp will have some CMRR, meaning a small amount of rumble might still be amplified with the music.

  • Ok, but what’s even the big difference between putting a shunt resistor on the low side vs the high side?

    • The common mode voltage (VCM) is literally the average of the two voltage inputs into the amplifier. VCM = (V1 + V2) / 2

    • Thus, when Rshunt is placed on the low side (and since the voltage drop across the shunt is negligible) VCM is far closer to GND

    • Conversely, if Rshunt is placed on the high side, VCM is far closer to Vsupply.

    • This means that using a high side shunt resistor will require an amplifier with a higher CMMR (common mode rejection ratio).

  • Ok, but then why not just put it on the low-side and go on with our lives?

    • Let’s say some system fault happens and the low side of Rshunt becomes grounded. Then, our system load never actually gets power! All of the current flows directly to ground.

    • With a low-side shunt resistor, this would never be detected, as we would just read in a Vshunt of zero or perhaps some floating voltage.

    • With a high-side shunt resistor, however, we read in a voltage of Vsupply, as the entire voltage drop happens across Rshunt.

    • This isn’t really a concern with our application as we don’t really care. If the user of this board happens to detect a fault condition, they will notice it immediately as their board will not get power.

  • Another issue is ground loops. The gist is that if some components on the system use one ground and some use another, there can be some path for current flow. Even if the grounds aren’t connected, there are many ways things can go wrong (for example, even things like stray electromagnetic fields can induce small currents).

    • In this case, the system load (the device being powered) would have a slightly higher ground reference than our buck converters or USB-PD chip, which means that we would need separate ground planes or paths.

    • On the other hand, if a high-side resistor is used, the grounds of everything is all the same, so no possibility of weird ground shit happening.

  • High-side shunt resistor is our answer then.

• To select a shunt resistor, we also have to keep in mind our amplifier circuitry due to something called amplifier offset voltage. https://www.allaboutcircuits.com/technical-articles/understanding-the-amplifier-offset-voltage-and-output-swing-in-resistive-current-sensing/

  • Let’s say the two inputs to our current sense amplifier are V+ and V-. Ideally, if V+ == V-, then Vout = 0V. However, this is not truly the case, and current sense amplifiers will have some necessary offset on V+ to be applied so that Vout = 0V.

• If Gdiff is differential gain of the amplifier:

  • Vout = Gdiff (VA - VB)

  • Since VA - VB = Vshunt + Voffset, Vout = Gdiff (Vshunt + Voffset)

• Next, let’s look at error. Error is defined as (Measured Value - Actual Value)/(Actual Value).

  • Measured value is Vshunt + Voffset (not including Gdiff as that is really just a multiplier for ADC measurement purposes)

  • Actual value is just Vshunt since that’s what we’re trying to measure

  • Therefore, Error = ((Vshunt + Voffset) - Vshunt)/(Vshunt)

  • If Vshunt = Voffset , then Error = ((Vshunt + Vshunt) - Vshunt)/Vshunt = Vshunt/Vshunt = 1 = 100%.

• This matters because it screws up our accuracy at lower current values (i.e. if Rshunt is fixed, and Voffset is fixed, and Ishunt is low enough, Vshunt >= Voffset)

  • Thus, we must find our lower bound for Vshunt, i.e. the shunt voltage that we are ok with 100% error because it is probably lower than minimum current of a device connected to the bus.

• On the mouser page Voffset is displayed as Vos for a given current sense amplifier.

  •  

  •  

Development

GITHUB LINK

Components and ICs:

Misc. Tips and Design Notes:

• Originally I was using the downloaded symbols for the MOSFETs when creating the schematic, but then I realized KiCad has a large base of existing symbols for common device configurations. For example, Device:Q_Dual_NMOS_S1G1S2G2D2D2D1D1 models an NMOS FET similar to the 12V Output N-Channel MOSFET.

  • Additionally, the MOSFET symbols you might download for one of these things will just look like a rectangle:

  • vs the KiCAD dual mosfet symbol (far clearer in what it actually is):

  • So using the symbols from the Device library for a MOSFET, and then linking it later to the downloaded footprint for the desired FET, will make the schematic clearer.

• This website is pretty good for resistor values:

  • Choose E24 for most commonly available values

• Originally I calculated inductors for max input of 20V, but in order to overspec it (as a safety measure) I’m going to redo the calculations for 25V and pick new inductors & ensure that the buck converters will still work as intended

• According to this presentation, the voltage tolerance on USB PD is +-5%. The undervoltage lockout points have been set at exactly these values so that we can ensure proper operation.

• Use wolfram alpha for conversions and calculations, it works pretty well.

• Murata (and many other manufacturers) caps may not provide the DC bias curves on the datasheet directly, but have external design tools linked on the Mouser or Digikey page that will have the specific curve for the selected cap.

  • Digikey will often have more resources than Mouser, so make sure to check there.

  • See this reddit comment:

    That's just an example graph to show that ferroelectric dielectrics are shit. You need to look at the curves for the specific part number capacitor, which is not always available.

    For specific capacitor Vbias curves, I tend to look on the Digikey product page, where it will often be linked.

    For Samsung caps, look for "Datasheets: LONG-MFG-PART-NO Characteristics". Example digikey page. Example characteristics datasheet.

    For TDK, look for "Datasheets: Character Sheet". Example.

    For Murata, look for "Design Resources: SimSurfing Design Tool". Example.

    For KEMET, look for "Design Resources: K-SIM Simulation". Example. There's a drop-down menu on the upper left to select "Capacitance vs. Vbias" plot.

    I'm pretty sure AVX has something similar, but not seeing an easy example, so no link. I guess they have crap coverage.

    I've never found a good link for Taiyo Yuden, though I haven't searched much.

    Wurth has a link that looks suspiciously like simulation results, but require you to signup and login, so fuck them. I'm not making an account to learn about your commodity passives.

    So the data is out there for like 25-50% of the ceramic caps on digikey. I just assume the rest are garbage and ignore them, but then again I don't have BOM price pressure forcing me to look for cheaper passives. It really should be a column on digikey's parametric sort: delta C @ 75% WV. But I think they have the same problem with data availability that we do.

  • Adding onto this, Taiyo Yuden has a product searcher that will give you similar characteristic sheets. Given that these are on the cheaper end of caps, having this sort of data on caps we use often is valuable.