Due Dates:

• Requirements/Considerations -

• Component Selection -

• Initial Schematic -

• Initial Layout -

• Rev. A Ordered -

• Firmware/Testing -

Charger Options:

Description/Purpose

• Key responsibilities to distribute the voltage to all the boards, LV MUX hat, PDU, and also have supp charging

Requirements

• Have a fail safe if SUPP fails shut off

• Have SUPP Charging TO

•  

Test plan

• Solder j13 to test LV-EN

• Solder J5 and F1 for supplemental battery inputs

• Supp ideal diode testing:

  • With the j13 headers off, put 24V into the J5

  • Verify supplemental battery voltage in rail is correct

  • SUPP_IN+ should be floating

  • Turn the power supply off

  • Connect j13 to the supplemental battery position

  • Put 24V into j5

  • Verify SUPP_IN+ == Supplemental_Bat_In

    • Run through the range of 18V - 33V

• Supplemental Vicor

  • Solder U4

  • Place vicor carrier in board, and ensure output is 24V

• LeaderSOM

  • Solder LeaderSOM connectors

  • Verify 3.3V is coming out of the LeaderSOM

• Supplemental Hall Effect

  • put supp power in with vicor carrier in

  • probe I_SNS_Reg_In, voltage should be around .33V

• V2 ideal diode testing

  • Solder J8

  • Verify that V2 (TP18) is always at 24V

  • Turn power off

  • move J13 into power supply position

  • put 24V into J13

  • make sure tp18 is still 24V

• post vicor supp hall effect should be I_SNS_Reg_Out is ~.33V

•  

• HV Testing

  • Solder J3 and F2

  • Solder U2

  • Place 120V into J3 and verify 24V is coming out of TP22

•  

Application Note

Needs to be in direct communication with the supp board to understand where to send the load

Context

Location of the board:

Connection List

Main

Schematics

Circuit Components

Layout

Github link:

PCB:

3D Model

Firmware

Drivers

High-Level (Block Diagram)

Testing:

R2 and R40 - Shunt Resistors, Wrong footprint on the board

R44, R1, R33, R1, Q6, D5 - Correctly soldered