Due Dates:

• Requirements/Considerations - 4/7/2025

• Component Selection - 4/12/2025

• Initial Schematic - 4/16/2025

• Initial Layout - 4/23/2025

• Rev. A Ordered - 4/26/2025

• Firmware/Testing - idk

  • Active Precharge Testing w/ Bulk Cap next workday

  • All enable out, precharge ready inputs and sense inputs work

Description/Purpose

controls the vehicle…

Requirements

• Contactor Control

  • Array/Array Precharge → BPS Leader (in BB)

    • Separate board sends isolated, LV signals with comparison values (taps) for precharge resistor

  • Motor/Motor Precharge → VCU (in PDE)

    • Separate board sends isolated, LV signals with comparison values (taps) for precharge resistor

  • Fail open - AND gate between software/hardware comparison

    • Hardware - current op-amp comparison

    • Software - isolated ADC

    • Precharge threshold at 91%, lower threshold of 81% for hysteresis

• Integration with driver controls

  • Motor Control

    • Bridge between CarCAN & MotorCAN

    • Translate pedal state, gear state to drive commands

      • Pedal board on CarCAN, display on CarCAN

    • Moore FSM for motor control, regen, cruise

      • VCU will run this FSM

  • Regen

    • What to expect from driver?

      • Selection of regen amount

        • Based on empirical testing

        • As a function of current speed/conditions

      • Regen at setpoint (ideally 100%) when accelerator/brake aren’t pressed

      • At low speeds → will not regen, driver must brake mechanically

        • Send display message when regen is ineffective (need testing data)

      • When brake is pressed - keep regen enabled? will just be less effective since no line lock

    • What edge cases + how to handle?

      • BPS close to charging temp threshold → depends on current

      • SoC too high - 95% (dependent on conditions)

      • Messages BPS ↔︎ VCU

        • BPS sends regen_disable message, if VCU doesn’t ACK, BPS trip

          • VCU sends global regen_state message, if regen_state still on after BPS sends disable + delay, BPS trip

        • If we continue regen past a certain point (97%), BPS sends regen_disable → must wait for SoC <95% to regen again

  • Ignition Sequence

    • Off, Motor, Array states

    • Controls Leader waits until IGN switch is back to OFF state before broadcasting array or motor

      • Prevents starting in motor/array state

  • Debugging

    • For both BPS Leader and VCU - ESP32 connected to LSOM UART for necessary debug messages

    • Wifi for connection - test with actual enclosures for signal

• Electrical

  • LSOM - what peripherals/pins needed?

    • two CANs

    • UART

    • GPIO

      • Motor Drive

      • Motor Sense

      • Motor Precharge Drive

      • Motor Precharge Sense

      • Motor Precharge Ready

  • Additional ICs/circuits for anything?

    • On precharge boards (2x) isolated ADCs

• Mechanical

  • Packaging

    • small

    • more square is better - spread out around LSOM

    • black, gold plated, high def silks

    • no monkey bullshit

    • Power Distribution Enclosure (PDE)

    • sizing/space??

  • Connections

    • CarCAN In/Out, MotorCAN Out (terminating end)

    • Signals from precharge board

      • Two ADC outputs

      • Signal from hardware comparator output

      • 12V - use 12V tolerant ICs

      • one connector on board

    • Two contactor 4 pin

      • drive+, drive-, sense+, sense-

Application Note

how does this board integrate with others + any harnessing/bringup considerations. anyone should be able to read this and integrate this board into the electrical system

Context

Location of the board: Power Distribution Enclosure (vertically behind driver)

Connection List

Main

Schematics

every subsheet here

Circuit Components

all uniques (non-passives) in BOM + rationale for selection

Layout

PCB

3D Model

Firmware

Drivers

High-Level (Block Diagram)

Meetings: